The clock-data recovery (CDR) circuitry based on a phase-lock loop (PLL) usually includes two loops. A first loop brings the frequency of the voltage-controlled oscillator (VCO) (e.g., the CDR frequency) closer to the frequency of the input data (e.g., the input frequency) while a second loop locks the phase of the VCO into that of the input data. In some approaches related to the two-loop structure using the spread spectrum clock (SSC), however, if the input frequency varies at the transition from the first loop to the second loop, the VCO does not lock into the input data. As a result, there is a need to solve the above problem.
Like reference symbols in the various drawings indicate like elements.